System Verification Engineers

Location- Cambridge – United Kingdom
Years of experience- 5+ Years
No sponsorship provided for this role
Preferred valid work permit candidates.

Key Responsibility

• End-to-end UVM verification flow including coverage closure
• Developing, Implementation, and maintaining UVM verification
• Good AXI protocol knowledge
• Some experience in C /C++ coding
• Contributing to the evolution and continuous improvement of our development processes
• Understanding of Verification development of well-constructed, reusable System Verilog
• based Verification environment and Planning Management methods skills
• Ensuring the overall quality of the released product (UVM)
• Planning and tracking tasks to meet the targets at the on-time deliverables
• Driving the execution to ensure the quality of the design work done along with on time delivery
• Coaching and mentoring junior engineers.

Skills Knowledge and Expertise

• System verification experience and candidate willing to take it up
• Cortex-M experience
• Understanding of cryptographic algorithms
• Knowledge of a scripting language
• Python programming experience.